A field programmable gate array (FPGA) comprises an array of programable logic blocks which can be programably interconnected to each other to provide a logic function desired by a user. U.S. Pat. No. 4,870,302, reissued as U.S. Pat. No. Re 34,363 to Ross Freeman describes the first FPGA, and is incorporated herein by reference. Later patents such as U.S. Pat. Nos. 4,758,745 to Elgamal, and 5,243,238 to Kean and published application WO 93/05577 invented by Furtek and owned by Concurrent Logic, Inc. describe other FPGA architectures. These patents and application are also incorporated herein by reference. The Xilinx 1994 Data Book entitled "The Programable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124 describes several products which implement FPGA architectures. As illustrated in the Xilinx 1994 Data Book at pages 2-111 through 2-117 and 2-187 through 2-190, incorporated herein by reference, FPGA products typically include a regular array of logic blocks, the number of which varies from one product to another. Long and short lines are available to interconnect logic blocks.
When a signal on a line must drive several loads, it is sometimes necessary to buffer the signal in the mid-portion of the line so that the signal will have sufficient strength to drive the required loads without being excessively slowed by the combination of the load and any resistance on the signal line. But for a field programmable device, the direction of signal flow on bidirectional long lines can not be determined at the time the device is manufactured because one user will program the device for signal flow in one direction along the line and another user will program the device for signal flow in another direction. For such flexibility, bidirectional buffers must be used. Hsieh in U.S. Pat. No. 4,835,418 [M-615] and Young in application Ser. No. 08/507,626 [X-195] (both incorporated herein by reference) describe bidirectional buffer having two control signals, which can buffer a signal in either of two directions between two line segments or can disconnect the two line segments (the tristate condition). The control signals can come from memory cells if the two line segments are to have a static directional relationship and the buffer direction is to remain constant.
Xilinx long lines can be accessed through tristate buffers so they can be used as bus lines. However, if two line segments are part of a single bus line to which input signals are applied from different sources at different times, the buffer direction may need to switch dynamically. Providing dynamic switching requires a control system more sophisticated than simply a pair of memory cells or other static signal sources.